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Verilog: Part – II | Electronic Design Automation | Video lecture

Verilog: Part – II


Topics in Video

Parameters

Logic Velues

Verilog provides a set of predefined logic gates.

Primitive Gates

Primitive Tri-State gates (instantiation)

Some Points to Note

timescale 1 ns/1ns

Hardware Modeling Issues

module reg_maps_to_wire (A, B, C, f1, f2);

module a_problem_case (A, B, C, f1, f2);

module reg_maps_to_wire (A, B, C, f1, f2);

// A latch gets inferred here

Verilog Operators

Reduction operators (operate on all the bits within a word)

module operator_example (x, y, f1, f2);

// An 8-bit adder description

Some Valid Statements

1:55

4:13

6:55

10:31

11:13

13:31

17:54

24:30

28:49

34:36

36:49

38:24

43:25

44:36

46:07

48:25

51:55

 

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